This inheritance list is sorted roughly, but not completely, alphabetically:
[detail level 12]
  active_controls | Slot for adding control lines automatically |
| BDDTable | Contains the result data for read_pla_to_bdd |
| bus_collection | Collection for buses |
| circuit | Main circuit class |
| control_line_adder | Helper class for adding lines in an easier way |
| copy_metadata_settings | Settings for copy_metadata |
| core_gate_simulation | A gate simulation implementation of gate_simulation_func |
 create_image_settings | Generic class for the create_image function (Template Design Pattern) |
 create_pstricks_settings | Implementation of create_image_settings for generating LaTeX code using PsTricks |
 create_tikz_settings | Implementation of create_image_settings for generating LaTeX code using TikZ |
| embed_and_synthesize | Concrete re-synthesis functor for the revkit::line_reduction algorithm |
| fredkin_tag | Target Tag for Fredkin gates |
| function | |
| functor< bool(binary_truth_table &, const binary_truth_table &)> | |
| functor< bool(boost::dynamic_bitset<> &, const circuit &, const boost::dynamic_bitset<> &)> | |
| functor< bool(circuit &, const binary_truth_table &)> | |
| functor< T > | Functor class for interfacing algorithms |
| gate | Represents a gate in a circuit |
| filtered_gate | Wrapper for a gate to filter some lines |
| gate_costs | Calculates the gate costs |
| graph_as_tree | |
| constructible_tree< Graph > | This class represents a tree based on a Boost.Graph |
| line_costs | Calculates the line costs |
| line_window_selection | Window Selection functor based on Line Window Selection |
| measure_method | Measure Method for timer |
| module_tag | Target Tag for Modules |
| options_description | |
| program_options | Class for program options on top of the Boost.Program_Options library |
| pattern | Pattern file for sequential simulation |
| peres_tag | Target Tag for Peres gates |
| print_circuit_settings | Settings for print_circuit function |
| print_statistics_settings | Settings for print_statistics |
| print_timer | Functor for the timer class which prints the run-time to an output stream |
| properties | Property Map for storing settings and statistical information |
| properties_timer | Functor for the timer class which assigns the run-time to a property map |
| quantum_costs | Calculates the quantum costs |
| read_pla_settings | Settings for read_pla function |
| reference_timer | Functor for the timer class which assigns the run-time to a given variable |
| resynthesis_optimization | Re-synthesis optimization (Wrapper for window_optimization) |
| revlib_processor | Base class for actions on the revlib_parser |
| circuit_processor | Implementation of revlib_processor to construct a circuit |
| specification_processor | Implementation of revlib_processor to construct a reversible_truth_table |
| shift_window_selection | Window Selection functor based on Shift Window Selection |
| standard_circuit | Represents a circuit |
| standard_decomposition | Default gate-wise decomposition |
| subcircuit | Represents a sub-circuit |
| target_line_adder | Helper class for adding lines in an easier way |
| timer< Outputter > | A generic timer class |
| toffoli_tag | Target Tag for Toffoli gates |
| transistor_costs | Calculates the transistor costs |
| truth_table< T > | Represents a truth table |
| v_tag | Target Tag for V gates |
| vplus_tag | Target Tag for V+ gates |
| weighted_reordering | Cubes reordering strategy as proposed in [FTR07] |
| write_blif_settings | Settings for write_blif |
| write_realization_settings | Settings for write_realization function |
| write_specification_settings | Settings for write_specification |
| write_verilog_settings | Settings for write_verilog |
