![]() ![]() | Main namespace |
![]() ![]() ![]() | Represents a circuit |
![]() ![]() ![]() | Represents a sub-circuit |
![]() ![]() ![]() | Main circuit class |
![]() ![]() ![]() | Slot for adding control lines automatically |
![]() ![]() ![]() | Helper class for adding lines in an easier way |
![]() ![]() ![]() | Helper class for adding lines in an easier way |
![]() ![]() ![]() | This class represents a tree based on a Boost.Graph |
![]() ![]() ![]() | Settings for copy_metadata |
![]() ![]() ![]() | Functor class for interfacing algorithms |
![]() ![]() ![]() | Represents a gate in a circuit |
![]() ![]() ![]() | Wrapper for a gate to filter some lines |
![]() ![]() ![]() | Generic class for the create_image function (Template Design Pattern) |
![]() ![]() ![]() | Implementation of create_image_settings for generating LaTeX code using PsTricks |
![]() ![]() ![]() | Implementation of create_image_settings for generating LaTeX code using TikZ |
![]() ![]() ![]() | Settings for print_circuit function |
![]() ![]() ![]() | Settings for print_statistics |
![]() ![]() ![]() | Settings for read_pla function |
![]() ![]() ![]() | Contains the result data for read_pla_to_bdd |
![]() ![]() ![]() | Implementation of revlib_processor to construct a circuit |
![]() ![]() ![]() | Implementation of revlib_processor to construct a reversible_truth_table |
![]() ![]() ![]() | Base class for actions on the revlib_parser |
![]() ![]() ![]() | Settings for write_blif |
![]() ![]() ![]() | Settings for write_realization function |
![]() ![]() ![]() | Settings for write_specification |
![]() ![]() ![]() | Settings for write_verilog |
![]() ![]() ![]() | Collection for buses |
![]() ![]() ![]() | Pattern file for sequential simulation |
![]() ![]() ![]() | Property Map for storing settings and statistical information |
![]() ![]() ![]() | Target Tag for Toffoli gates |
![]() ![]() ![]() | Target Tag for Fredkin gates |
![]() ![]() ![]() | Target Tag for Peres gates |
![]() ![]() ![]() | Target Tag for V gates |
![]() ![]() ![]() | Target Tag for V+ gates |
![]() ![]() ![]() | Target Tag for Modules |
![]() ![]() ![]() | Represents a truth table |
![]() ![]() ![]() | Calculates the gate costs |
![]() ![]() ![]() | Calculates the line costs |
![]() ![]() ![]() | Calculates the quantum costs |
![]() ![]() ![]() | Calculates the transistor costs |
![]() ![]() ![]() | Class for program options on top of the Boost.Program_Options library |
![]() ![]() ![]() | Functor for the timer class which prints the run-time to an output stream |
![]() ![]() ![]() | Functor for the timer class which assigns the run-time to a given variable |
![]() ![]() ![]() | Functor for the timer class which assigns the run-time to a property map |
![]() ![]() ![]() | Measure Method for timer |
![]() ![]() ![]() | A generic timer class |
![]() ![]() ![]() | Concrete re-synthesis functor for the revkit::line_reduction algorithm |
![]() ![]() ![]() | Window Selection functor based on Shift Window Selection |
![]() ![]() ![]() | Window Selection functor based on Line Window Selection |
![]() ![]() ![]() | Re-synthesis optimization (Wrapper for window_optimization) |
![]() ![]() ![]() | A gate simulation implementation of gate_simulation_func |
![]() ![]() ![]() | Cubes reordering strategy as proposed in [FTR07] |
![]() ![]() ![]() | Default gate-wise decomposition |