![]() ![]() | Slot for adding control lines automatically |
![]() ![]() | Prepending, inserting and appending circuits to another circuit |
![]() ![]() | Adding typical gates to a circuit |
![]() ![]() | Add a line to a circuit with specifying all meta-data |
![]() ![]() | Adding Lines Optimization |
![]() ![]() | BDD Based Synthesis |
![]() ![]() | Bus Collection |
![]() ![]() | Circuit class |
![]() ![]() | Returns the hierarchy of a circuits by its modules |
![]() ![]() | Generates a truth table from a circuit |
![]() ![]() | Clears a circuit |
![]() ![]() | Gets the control lines of a gate |
![]() ![]() | Copies a circuit |
![]() ![]() | |
![]() ![]() | Cost calculation for circuits |
![]() ![]() | LaTeX functions for printing circuits |
![]() ![]() | Create simulation pattern for sequential simulation |
![]() ![]() | Embedding of an irreversible specification |
![]() ![]() | SAT-based equivalence check (respects garbage outputs and constant inputs) |
![]() ![]() | ESOP Based Synthesis |
![]() ![]() | Exact Synthesis of Reversible Networks |
![]() ![]() | Expand a circuit on the base of a sub circuit |
![]() ![]() | Removes the Don't Care Values of a binary truth table |
![]() ![]() | Finds empty and non-empty lines in circuits and gates |
![]() ![]() | Flattens a circuit with modules |
![]() ![]() | Determines whether a truth_table is fully specified |
![]() ![]() | Generic Functor Implementation based on Boost.Function |
![]() ![]() | Gate class |
![]() ![]() | KFDD Based Synthesis |
![]() ![]() | Line Reduction Optimization |
![]() ![]() | Linear nearest Neighbor |
![]() ![]() | General Optimization type definitions |
![]() ![]() | Simulation considering constant inputs and garbage outputs |
![]() ![]() | Data Structure for Simulation Pattern |
![]() ![]() | Console output of a circuit |
![]() ![]() | Print statistics about a circuit |
![]() ![]() | Easier access to program options |
![]() ![]() | Property Map Implementation for Algorithms |
![]() ![]() | Quantum Decomposition of Reversible Circuits |
![]() ![]() | Parser for Simulation pattern |
![]() ![]() | Reads a specification from a PLA file |
![]() ![]() | Reads a BDD from a PLA file |
![]() ![]() | Parser for RevLib realization (*.real) file format |
![]() ![]() | Parser for RevLib specification (*.spec) file format |
![]() ![]() | Synthesis algorithm based on Reed Muller Spectra |
![]() ![]() | Reverse a circuit |
![]() ![]() | RevLib file format parser |
![]() ![]() | Processor which works with the revlib_parser |
![]() ![]() | Sequential Simulation considering state inputs |
![]() ![]() | Very simple simulation, only efficient for small circuits |
![]() ![]() | General Simulation type definitions |
![]() ![]() | SWOP - Synthesis With Output Permutation |
![]() ![]() | General Synthesis type definitions |
![]() ![]() | Gets the target lines of a gate |
![]() ![]() | Predefined target type tags for common gate types |
![]() ![]() | A generic way for measuring time |
![]() ![]() | Transformation Based Synthesis |
![]() ![]() | A simple synthesis algorithm based on transpositions |
![]() ![]() | A simple synthesis algorithm based on transpositions |
![]() ![]() | Class for truth table representation |
![]() ![]() | General Verification type definitions |
![]() ![]() | Returns RevKit version |
![]() ![]() | Window Optimization |
![]() ![]() | Writes a circuit to a BLIF file |
![]() ![]() | Generator for RevLib realization (*.real) format |
![]() ![]() | Writes a truth table to a RevLib specification file |
![]() ![]() | Writes a circuit to a Verilog file |