Overview

This page gives an outline of all components in the libraries.

Core

gate	Gate class
circuit	Circuit class
functor	Generic Functor Implementation based on Boost.Function.
pattern	Data Structure for Simulation Pattern
properties	Property Map Implementation for Algorithms
target_tags	Predefined target type tags for common gate types new features
truth_table	Class for truth table representation
version	Returns RevKit version
Functions
active_controls	Slot for adding control lines automatically
add_circuit	Prepending, inserting and appending circuits to another circuit
add_gates	Adding typical gates to a circuit
add_line_to_circuit	Add a line to a circuit with specifying all meta-data
circuit_hierarchy	Returns the hierarchy of a circuits by its modules
circuit_to_truth_table	Generates a truth table from a circuit
clear_circuit	Clears a circuit
control_lines	Gets the control lines of a gate
copy_circuit	Copies a circuit
copy_metadata	Settings for copy_metadata
create_simulation_pattern	Create simulation pattern for sequential simulation
expand_circuit	Expand a circuit on the base of a sub circuit
extend_truth_table	Removes the Don't Care Values of a binary truth table
find_lines	Finds empty and non-empty lines in circuits and gates
flatten_circuit	Flattens a circuit with modules
fully_specified	Determines whether a truth_table is fully specified
reverse_circuit	Reverse a circuit
target_lines	Gets the target lines of a gate
transposition_to_circuit	A simple synthesis algorithm based on transpositions new features
I/O
create_image	LaTeX functions for printing circuits
print_circuit	Console output of a circuit
print_statistics	Print statistics about a circuit
read_pattern	Parser for Simulation pattern
read_realization	Parser for RevLib realization (*.real) file format
read_specification	Parser for RevLib specification (*.spec) file format
read_pla	Reads a specification from a PLA file
revlib_parser	RevLib file format parser
revlib_processor	Processor which works with the revlib_parser
write_blif	Writes a circuit to a BLIF file new features
write_realization	Generator for RevLib realization (*.real) format
write_specification	Writes a truth table to a RevLib specification file
write_verilog	Writes a circuit to a Verilog file
Meta
bus_collection	Bus Collection
Utils
costs	Cost calculation for circuits
program_options	Easier access to program options
timer	A generic way for measuring time

Algorithms

Optimization
adding_lines	Adding Lines Optimization
line_reduction	Line Reduction Optimization
window_optimization	Window Optimization
Synthesis
bdd_synthesis	BDD Based Synthesis
embed_truth_table	Embedding of an irreversible specification
esop_synthesis	ESOP Based Synthesis
exact_synthesis	Exact Synthesis of Reversible Networks
kfdd_synthesis	KFDD Based Synthesis
quantum_decomposition	Quantum Decomposition of Reversible Circuits
reed_muller_synthesis	Synthesis algorithm based on Reed Muller Spectra new features
swop	SWOP - Synthesis With Output Permutation
transformation_based_synthesis	Transformation Based Synthesis
transposition_based_synthesis	A simple synthesis algorithm based on transpositions new features
Simulation
partial_simulation	Simulation considering constant inputs and garbage outputs
sequential_simulation	Sequential Simulation considering state inputs
simple_simulation	Very simple simulation, only efficient for small circuits
Verification
equivalence_check	SAT-based equivalence check (respects garbage outputs and constant inputs)