References

[SWD10] M. Soeken, R. Wille, and R. Drechsler, Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition, International Design and Test Workshop, pages 143-148, 2010.

[WSD10] R. Wille, M. Soeken, and R. Drechsler, Reducing the Number of Lines in Reversible Circuits, Design Automation Conference, pages 647-652, 2010.
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[MWD10] D. M. Miller, R. Wille, and R. Drechsler, Reducing Reversible Circuit Cost by Adding Lines, International Symposium on Multiple-Valued Logic, pages 647, 2010.

[SWDD10] M. Soeken, R. Wille, G. W. Dueck, and R. Drechsler, Window Optimization of Reversible and Quantum Circuits, International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 431-435, 2010.
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[WD09] R. Wille and R. Drechsler, BDD-based synthesis of reversible logic for large functions, Design Automation Conference, pages 270-275, 2009.
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[GWDD09] D. Große, R. Wille, G. W. Dueck, and R. Drechsler, Exact Multiple Control Toffoli Network Synthesis with SAT Techniques, IEEE Trans. on CAD, pages 703-715, 2009.

[WGDD09] R. Wille, D. Große, G. W. Dueck, and R. Drechsler, Reversible Logic Synthesis with Output Permutation, International Conference on VLSI Design, pages 189-194, 2009.
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[WGMD09] R. Wille, D. Große, D. M. Miller, and R. Drechsler, Equivalence Checking of Reversible Circuits, International Symposium on Multi-Valued Logic, pages 324-330, 2009.
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[FTR07] K. Fazel, M. A. Thornton, and J. E. Rice, ESOP-based Toffoli Gate Cascade Generation, In IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pages 206-209, 2007.

[MDM07] D. Maslov, G. W. Dueck, and D. M. Miller, Techniques for the synthesis of reversible Toffoli networks, In ACM Transactions on Design Automation of Electronic Systems, Volume 12, Issue 4, Article 42, 2007.

[MMD03] D. M. Miller, D. Maslov, and G. W. Dueck, A Transformation Based Algorithm for Reversible Logic Synthesis, Design Automation Conference, pages 318-323, 2003.

[MD03] D. Maslov and G. W. Dueck, Improved quantum cost for n-bit Toffoli gates, In Electronic Letters 39(25), pages 1790-1791, 2003.

[BBC+95] A. Barenco, C. H. Bennett, R. Cleve, D. P. DiVincenzo, N. Margolus, P. Shor, T. Sleator, J. A. Smolin, and H. Weinfurter, Elementary gates for quantum computation, In Physical Review A 52(5), pages 3457-3467, 1995.