ETS 2018

Organizers:
René Krenz-Baath - Hamm-Lippstadt University (UAS)
Artur Jutman - Testonica Lab

The TESTA workshop is a focused, open discussion platform dedicated to exchange of fresh ideas, industry best practices, methodologies and work-in progress around chip test, board test and system test related standards, especially those being actively developed today or the ones recently released. Contributions covering IEEE 1149.x, IEEE 500, IEEE 1687, IEEE P1838, IEEE 1450, and others are anticipated. Particularly welcome are contributions that discuss what works, what does not, or how the standards were incorporated into existing or upcoming DFT methodologies. Reports on first-time usage of new and upcoming standards are welcome, as is research exploring the best usage of features described in these standards. Cyber security aspects in the area of test are of special interest at this year's workshop.

Website: https://www.hshl.de/en/testa2018/

Organizers:
Giorgio Di Natale (LIRMM, FR)
Francesco Regazzoni (ALARI, IT)

Relationship between reliability/testability and security is contradictory: reliability addresses issues related with malfunctioning of devices which might naturally happen, while security aims at defeating malicious attempts of altering the normal behavior of a device. While techniques from one domain can be applied to the other, requirements of one domain can be in significant contrast with the second one. Besides these issues, with the advance of new research directions such as IoT, Wearable Devices, Cyber Physical Systems, and Autonomous driving, a set of additional properties have to be guaranteed in future devices, including safety, trust and privacy. Even more than before, requirements of one property can be in significant contrast with another one. The proposed workshop addresses this problem aiming at bringing together the involved communities to foster fruitful discussions and collaborations among researchers.

Website: http://www.lirmm.fr/surrealist18/

Organizers:
Alberto Bosio (LIRMM, FR)
Mario Barbareschi (DIETI, IT)

Approximate Computing leverages the intrinsic error resilience of applications to inaccuracy in their inner calculations, in order to achieve a required trade-off between efficiency, in terms of performance and power demanding, and acceptable error of returned results. In particular, for audio, image and video processing, data mining and information retrieval, approximate results turn out hard to distinguish from perfect ones. In recent years, Approximate Computing applicability is broadening and it has been representing a breakthrough in many scientific areas. Suitable solutions comes from approximate arithmetic operators, implemented both at hardware and software level, but from unreliable memory architectures, integrated circuit test, compilers and many others. The aim of this workshop is the investigation of connections between AxC paradigm and the verification, the test and the reliability of digital circuits from two points of view: (i) how the approximate computing paradigm impacts the design and manufacturing flow of integrated circuits, and (ii) how the verification, testing and reliability disciplines can be exploited in the approximate computing paradigms.

Website: http://www.lirmm.fr/axc18/