16th International Workshop on Boolean Problems | Times are in CEST (Central European Summer Time)

Program

University of Bremen | MZH 1090

Wednesday | September 18


17:00 - 18:30 Welcome Reception


Thursday | September 19


9:15 - 9:45 Registration

9:45 - 10:00 Opening
Chair: Rolf Drechsler

10:00 - 11:00 | Keynote 1
Chair: Görschwin Fey

Prof. Jan Peleska
Universität Bremen

Scary or Promising ? Machine Learning in Safety-Critical Control Systems

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11:00 - 11:30 | Coffee Break

11:30 - 12:30 | Session 1 | Logic Synthesis
Chair: Bernd Steinbach

On Structural Bias of Two-Level Multi-Output Minimization
Petr Fišer and Jan Schmidt

PSOP Decomposition for EXOR-Based Synthesis
Anna Bernasconi, Valentina Ciriani, Gianmarco Cuciniello and Asma Taheri Monfared


12:30 - 13:30 | Lunch

13:30 - 15:00 | Session 2 | Approximate Circuits
Chair: Danila Gorodecky

Approximate LUT Count Reduction via Probabilistic Error Propagation
Thomas Schlögl and Oliver Keszocze

EnR: Extend and Reduce Methodology to Enable Formal Verification of Truncated Adders
Chandan Kumar Jha, Khushboo Qayyum, Muhammad Hassan and Rolf Drechsler

Detailed Insight into Approximate Circuits with Error-Responsive Information Flow Tracking
Lutz Schammer, Gianluca Martino, Amir Najafi, Alberto Garcia-Ortiz and Goerschwin Fey
15:00 - 15:30 | Coffee Break

15:30 - 16:30 | Special Session
Chair: Rolf Drechsler

Self-Explaining Digitally Controlled Systems

Speakers:
Martin Fränzle (Carl von Ossietzky University of Oldenburg),
Verena Klös (Carl von Ossietzky University of Oldenburg),
Rainer Koschke (University of Bremen)

17:00 - 22:00 | Social Event

Friday | September 20







9:00 - 10:00 | Keynote 2
Chair: Rolf Drechsler

Lars Hedrich
Johann Wolfgang Goethe-Universität, Frankfurt am Main

Synthesizing Analog Neural Networks for Low-Power AI

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10:00 - 11:00 | Keynote 3
Chair: Rolf Drechsler

Christoph Lüth
DFKI, Germany

The case for open source hardware

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11:00 - 11:15 | Coffee Break


11:15 - 12:15 | Session 3 | Games
Chair: Oliver Keszözce

Rectangle-free Four-colored Square Grids Realized by Cyclic-rotated Reusable Patterns
Bernd Steinbach
Why Less is Sometimes More – Using Boolean Literals to Solve 2048
Bernhard J. Berger, Christina Plump and Rolf Drechsler


12:15 - 13:15 | Lunch


13:15 - 14:15 | Session 4 | Design & Verification
Chair: Bernhard J. Berger

Two Approaches for Multipliers Design
Danila Gorodecky
SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth
Luca Mueller and Rolf Drechsler


14:15 - 14:30 | Closing
Chair: Görschwin Fey, Rolf Drechsler