November 04, 2021: 8:20 am 01:05 pm
Organizers:
Yingyan (Celine) Lin - Rice University, USA
Yanzhi Wang - Northeastern University, USA
In recent years, machine/deep learning algorithms has unprecedentedly improved the accuracies in practical
recognition and classification tasks, some even surpassing human-level accuracy. While significant progresses
have been made on accelerating the models for real-time inference on edge and mobile devices, the training of
the models largely remains offline on server side. State-of-theart learning algorithms for deep neural
networks (DNN) imposes significant challenges for hardware implementations in terms of computation, memory,
and communication. This is especially true for edge devices and portable hardware applications, such as
smartphones, machine translation devices, and smart wearable devices, where severe constraints exist in
performance, power, and area.
There is a timely need to map the latest complex learning algorithms to custom hardware, in order to achieve
orders of magnitude improvement in performance, energy efficiency and compactness. Exemplary efforts from
industry and academia include many application-specific hardware designs (e.g., xPU, FPGA, ASIC, etc.).
Recent progress in computational neurosciences and nanoelectronic technology, such as emerging memory
devices, will further help shed light on future hardwaresoftware platforms for learning on-a-chip. At
the same time new learning algorithms need to be developed to fully explore the potential of the hardware
architecture.
The overarching goal of this workshop is to explore the potential of on-chip machine learning, to reveal
emerging algorithms and design needs, and to promote novel applications for learning. It aims to establish
a forum to discuss the current practices, as well as future research needs in the aforementioned fields.
| 11:00am - 11:05am | Opening and Introduction |
| 11:05am - 11:50am | Keynote Talk 1
Session Chair: Yingyan (Celine) Lin, Rice University
Light in AI: Toward Efficient and Robust Neurocomputing with Optical Neural Networks
David Pan, The University of Texas at Austin |
| 11:50am - 1:05pm | Session 1: Session Chair: Yingyan (Celine) Lin, Rice University
Session Chair: Yingyan (Celine) Lin, Rice University |
| 11:50am - 12:15pm | Efficient Audio-Visual Understanding on AR Devices
Meng Li, Facebook |
| 12:15pm - 12:40pm | Privacy in Federated Learning at Scale
Peter Kairouz, Google |
| 12:40pm - 1:05pm | Co-Design for Low-Bitwidth Neural Networks with Dynamic Quantization
Zhiru Zhang, Cornell University |
| 1:05pm - 1:25pm | Break |
| 1:25pm - 2:40pm | Session 2: Hardware-award Deep Learning Techniques
Session Chair: Yingyan (Celine) Lin, Rice University |
| 1:25pm - 1:50pm | The Lottery Ticket Hypothesis: On Sparse, Trainable Neural Networks
Jonathan Frankle, Massachusetts Institute of Technology |
| 1:50pm - 2:15pm | Intelligent Visual Computing
Yuhao Zhu, University of Rochester |
| 2:15pm - 2:40pm | Algorithm and Hardware Co-Design for Efficient Deep Learning: Sparse and Low-rank Perspectives
Bo Yuan, Rugster University |
| 2:40pm - 3:25pm | Keynote Talk 2
Session Chair: Yanzhi Wang, Northeastern University
Democratizing TinyML: Generalization, Standardization and Automation
Vijay Janapa Reddi, Harvard University |
| 3:30pm - 4:45pm | Session 3: Emerging Device and Neuromorphic Computing
Session Chair: Yanzhi Wang, Northeastern University |
| 3:30pm - 3:55pm | NeuroSim Benchmark Framework
Shimeng Yu, Georgia Institute of Technology |
| 3:55pm - 4:20pm | Memristive devices and arrays for computing
Jianhua Yoshua Yang, University of Southern California |
| 4:20pm - 4:45pm | Secure and Efficient Deep Learning Computing-in-Memory, A Software and Hardware Co-Design Perspective
Deliang Fan, Arizona State University |
Website:
https://sites.google.com/rice.edu/iccad-halo-21/
