RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
Universität Bremen References Cite RevLib Acknowledgements About RevLib
Flattened ALU (alu_flat)

An arithmetic logic unit (including addition, subtraction, multiplication, and division) with a flattened control structure.

Download: alu_flat_239.src

Circuit Realizations:

Lib. lines gates costs File Pic. Ref. Notes
MCT+MCF 118 3671 181662 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 16 bit
MCT+MCF 230 14471 1380526 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 32 bit
MCT+MCF 182 3795 146496 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines; 16 bit
MCT+MCF 358 14723 1230784 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines; 32 bit
MCT+MCF 67 7286 363012 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 16 bit
MCT+MCF 131 28822 2760420 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 32 bit
MCT+MCF 119 3761 38657 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 16 bit
MCT+MCF 231 14657 158241 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 32 bit
MCT+MCF 183 3851 35263 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 16 bit
MCT+MCF 359 14843 151135 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 32 bit
MCT+MCF 68 7466 77002 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 16 bit
MCT+MCF 132 29194 315850 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 32 bit
 
legend

 back